1. Field of the Invention
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to an ultra-thin semiconductor package having a supporter that prevents warpage of the semiconductor package and a method of manufacturing the same.
2. Description of the Related Art
Smaller and thinner semiconductor packages such as a chip scale package, a micro ball grid array package, and an ultra-thin semiconductor package have recently been developed.
An ultra-thin semiconductor package is disclosed in U.S. Pat. No. 6,395,579. The structure of an ultra-thin semiconductor package will now be described.
FIG. 1 is a cross-sectional view of a conventional semiconductor package 100 having a through hole.
Referring to FIG. 1, a circuit board 10 has a through hole 12 with a size similar to a chip and a semiconductor chip 30 is located in the through hole 12. The semiconductor chip 30, which is located in the through hole 12, is electrically connected to a circuit pattern 18 of the circuit board 10. Predetermined portions of the semiconductor chip 30 and the circuit board 10 are molded by an epoxy molding compound (EMC) 50 composed of a resin material. In addition, a conductive ball 60 is attached to a lower surface of the circuit board 10.
The semiconductor package 100 can have a thickness similar to the height of the semiconductor chip 30.
A resin material is generally used for the EMC 50, covering predetermined portions of the semiconductor chip 30 and predetermined portions of the circuit board 10.
The EMC 50 is formed by spreading the resin material on the semiconductor chip 30 and the circuit board 10 and then curing the resin material at a predetermined temperature. The EMC 50 contracts in the curing process.
However, as is well known to those skilled in the art, the EMC 50 formed of the resin material and the semiconductor chip 30 formed of a silicon material have different thermal expansion coefficients, and thus, they contract by different amounts in the curing process. Therefore, as illustrated by W in FIG. 1, the semiconductor chip 30 and the EMC 50 may warp due to the relatively low contraction rate of the semiconductor chip 30. This is called warpage.
A degree of warpage d of the semiconductor chip 30 and the EMC 50 may be 100 to 400 μm. The warpage causes the height of the semiconductor package to increase. Thus, an ultra-thin semiconductor package would not be obtained. Furthermore, cracks may occur due to the warpage of the semiconductor package.